----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:50:46 03/12/2012 
-- Design Name: 
-- Module Name:    koppeling_test_uart - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library WORK;
use WORK.UART_PACK.all;

entity koppeling_test_uart is
	port(  	RX : in std_logic;
				TX : out std_logic;
				clk : in std_logic;
				Reset : in std_logic);	
end koppeling_test_uart;

architecture Structural of koppeling_test_uart is
	
component Read_UART_RAM is
	port(	Data_in : in std_logic_vector (7 downto 0);
			Reset, Klok, Buffer_full, Data_present	: in std_logic;
			read_buffer, Write_RAM, Done : out std_logic;
			Adres_RAM : out std_logic_vector (3 downto 0);
			Data_RAM	: out std_logic_vector (7 downto 0));			
end component;

component RAM_16x8 is 
	Port ( Clk : in std_logic; 
		Write_En : in std_logic; 
		Write_ADDR : in std_logic_vector(3 downto 0); 
		Read_ADDR : in std_logic_vector(3 downto 0); 
		Read_ADDR_2 : in std_logic_vector(3 downto 0); 
		Write_DATA : in std_logic_vector(7 downto 0); 
		Read_DATA : out std_logic_vector(7 downto 0);
		Read_DATA_2 : out std_logic_vector(7 downto 0));
end component;		
	
component totaal_uart is
	port(
--RX			
					 RX_serial_in : in std_logic;
					  RX_data_out : out std_logic_vector(7 downto 0);
				  RX_read_buffer : in std_logic;
				 RX_reset_buffer : in std_logic;
				 --RX_en_16_x_baud : in std_logic;
		RX_buffer_data_present : out std_logic;
				  RX_buffer_full : out std_logic;
			RX_buffer_half_full : out std_logic;
--TX 
						TX_data_in : in std_logic_vector(7 downto 0);
             TX_write_buffer : in std_logic;
             TX_reset_buffer : in std_logic;
             --TX_en_16_x_baud : in std_logic;
               TX_serial_out : out std_logic;
               TX_buffer_full : out std_logic;
         TX_buffer_half_full : out std_logic;
							    clk : in std_logic);
end component;
	
signal Data : std_logic_vector(7 downto 0);
signal RAM_W_ADDR : std_logic_vector(3 downto 0);
signal RAM_W_DATA : std_logic_vector(7 downto 0);
signal Done, Data_1_RX, Data_16_RX, RAM_W_EN, R_FIFO : std_logic;	 


begin

	Inst_Read_UART_RAM: Read_UART_RAM PORT MAP(
		Data_in => Data,
		Reset => reset,
		Klok => clk,
		Buffer_full => Data_16_RX,
		Data_present => Data_1_RX,
		read_buffer => R_FIFO,
		Write_RAM => RAM_W_EN,
		Done => Done,
		Adres_RAM => RAM_W_ADDR,
		Data_RAM => RAM_W_DATA
	);
	
		Inst_RAM_16x8: RAM_16x8 PORT MAP(
		Clk => clk,
		Write_En => RAM_W_EN,
		Write_ADDR => RAM_W_ADDR,
		Read_ADDR => (others => '0'),
		Read_ADDR_2 => (others => '0'),
		Write_DATA => RAM_W_DATA,
		Read_DATA => open,
		Read_DATA_2 => open
	);
	
	Inst_totaal_uart: totaal_uart PORT MAP(
		RX_serial_in => RX,
		RX_data_out => Data,
		RX_read_buffer => R_FIFO,
		RX_reset_buffer => reset,
		RX_buffer_data_present => Data_1_RX,
		RX_buffer_full => Data_16_RX,
		RX_buffer_half_full => open,
		TX_data_in => (Others => '0'),
		TX_write_buffer => '0',
		TX_reset_buffer => reset,
		TX_serial_out => TX,
		TX_buffer_full => open,
		TX_buffer_half_full => open,
		clk => clk
	);

end Structural;